Non-volatile memory devices are both electrically erasable and programmable. Such devices retain data even after the power to the device is terminated. One particular type of non-volatile memory device is the (electrically-erasable-programmable-read-only-memory) EEPROM device. In an EEPROM device, programming and erasing is accomplished by transferring electrons to and from a floating-gate electrode through a thin dielectric layer, known as a tunnel-oxide layer, located between the floating-gate electrode and the underlying substrate. Typically, the electron transfer is carried out either by hot electron injection, or by Fowler-Nordheim tunneling. In either electron transfer mechanism, a voltage is coupled to the floating-gate electrode by a control-gate electrode, which can be a region in a substrate known as a programming region. The control-gate electrode or programming region is capacitively coupled to the floating-gate electrode, such that a voltage applied to the programming region is coupled to the floating-gate electrode.
Single poly EEPROM cells are extensively used in programmable logic devices (PLDs). EEPROM cells used in PLDs can have a two-transistor design or a three-transistor design. A three transistor EEPROM cell, for example, includes a write transistor, a read transistor, and a floating-gate (or sense) transistor. In a two-transistor device, the functions of floating-gate and sense transistors are combined into a single transistor.
To program PLD EEPROMs, a high voltage Vpp+ is applied to the gate electrode of the write transistor and a relatively lower voltage Vpp is applied to the drain (bit line contact) of the write transistor. The voltage applied to the write transistor gate electrode turns the write transistor on allowing the voltage applied to the bit line to be transferred to the source of the write transistor. Electrons on the floating-gate electrode are drawn from the floating-gate electrode across a tunnel oxide layer to the source of the write transistor, leaving the floating-gate electrode at a high positive potential. The application of such high voltage levels is a write condition that results in a net positive charge being stored in the EEPROM cell.
To erase the EEPROM cell, a voltage Vcc is applied to the gate of the write transistor and ground potential is applied to the bit line and a high voltage Vpp+ is applied to the programming region. Under this bias condition, the high voltage applied to programming region is coupled to the floating-gate electrode and the EEPROM cell is erased by the transfer of electrons from the substrate across the tunnel oxide layer to the floating-gate electrode.
The efficient application of high voltage to the write transistor and sense transistor during program and erase cycles requires that the gate dielectric layers of these transistor have a similar thickness to the dielectric layer separating the program junction regions (which comprise a tunnel region and a programming region in the substrate) from the overlying floating-gate electrode. High voltage circuit elements, such as program transistors and sense transistors, are usually formed on a wafer substrate with a relatively thick gate oxide layer. Such relatively thick gate oxide layers are usually required to prevent transistor circuit breakdown in such a high-voltage operating environment. On the other hand, it is preferable that the low voltage circuitry, such as read transistors, be fabricated with relatively thin gate oxide layers on the substrate. Such thin gate oxide layers typically increase the speed of such circuit elements. For example, transistor elements having relatively short gate lengths and thin oxide layers typically provide increased operating speeds.
As process technologies evolve toward shorter and shorter gate lengths it is desirable to reduce the thickness of the gate oxide layer even further in order to achieve greater operating speed. Some circuit elements, however, may not be scalable. For example, because of significant endurance and data retention problems, tunnel oxide layers usually cannot be scaled down in thickness in the same manner as low voltage oxide layers. Such tunnel oxide layers may be thinner than high voltage oxide layers on the wafer substrate. Therefore, non-volatile memories can usually benefit from the formation of at least three differing oxide thicknesses on the same substrate. Accordingly, transistors with relatively thick oxide layers can accommodate high voltage program and erase operations, while read transistors and logic transistors, with relatively thin oxide layers, can operate at high speed with relatively thin gate oxides.
The fabrication of three separate oxide thickness requires several processing steps and increases the cost of manufacturing the device. Accordingly, EEPROM devices and, in particular, PLDs will benefit from a design strategy that eliminates the need for the fabrication of three separate oxide layers.